1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to structure and method for implementing diagnostic integrated circuits on a semiconductor wafer.
2. Description of the Related Art
Testing has been an integral component of semiconductor processing since the development of the earliest germanium-based bipolar integrated circuits. The need for testing then and now stems from both engineering and economic considerations. Circuit designers must be able to verify that circuits designed on paper and simulated on computer, work as intended when implemented in actual silicon. Similarly, process engineers must be able to track the behavior of the multitude of individual process steps used to fabricate a given integrated circuit. From an economic standpoint, it is critical for semiconductor manufacturers to be able to quickly pinpoint the origin of unacceptable yields so that the circuit design or the fabrication process may be altered as necessary without needlessly wasting lots of wafers that may cost several hundred thousand dollars or more.
Electrical and process verification testing of most integrated circuits is provided by test structures that are incorporated into a semiconductor wafer during the process of fabricating the various operational integrated circuits (e.g., microprocessors, random access memories, etc.) thereon. The test structures are designed to provide electrical verification test data on various components of the operational integrated circuits as well as verification of many of the myriad of process steps performed during the fabrication of the operational integrated circuits. In modem test structures, well over a hundred or more different types of parameters are routinely captured by the test structures.
Early test structures consisted of individual die commonly known as process control monitors ("PCM") that were placed in various die locations across the face of a given wafer and fabricated in concert with the surrounding operational integrated circuits. This type of test structure prevailed throughout the period of semiconductor manufacturer when 1.times. reticles were used for direct print or contact printing or projection scanning of semiconductor devices. Early in the last decade, the semiconductor industry transitioned away from 1.times. reticle processing in favor of lithographic stepping. As a consequence, PCMs as test structures were largely abandoned in favor of scribe line monitors ("SLM").
There are several disadvantages associated with conventional structures and methods for implementing PCMs and SLMs. In the conventional design and fabrication of PCMs, little attention has been paid to the tailoring of the configuration of a given PCM relative to surrounding operational integrated circuits or the particular dispersal of PCMs across the face of a given wafer. Manufacturing experience has demonstrated that the differences in the structural densities of the PCM and the surrounding operational integrated circuits can significantly degrade the yield of those operational integrated circuits that do surround a particular PCM. The differential structural density between a given PCM and the operational integrated circuits that surround it impacts the behavior of various etch and polish steps that are performed on the wafer. A given conventional PCM typically has a much lower structural density, that is, number and/or size of physical structures, e.g. gates, metallization lines, isolation structures, etc. per unit area than the surrounding operational integrated circuits, which typically have many more circuit devices and structures per unit area. As a result, etchants and polish solvents may be more aggressively consumed by the less structurally dense areas in the PCM than in the surrounding operational integrated circuits, resulting in inadequate etching and/or polishing of certain structures in the operational integrated circuits. The problem of differential structural density is further compounded by the fact that the die borders for conventional PCMs are routinely much larger than the die borders for the surrounding operational integrated circuits.
Conventional SLMs do not present the same types of yield problems associated with conventional PCMs. However, conventional SLMs often cannot provide sufficient electrical data. The problem is primarily one of packing density. SLMs are, as the name implies, fabricated in the scribe lines. Space is accordingly limited. As die sizes have increased to accommodate more complex circuits, the number of different test parameters and thus SLMs that are required has increased proportionally. However, it is frequently difficult to pack the requisite number of SLMs into the confined spaces of the scribe lines. Thus, compromises in the amount of date gathered must be made.
Another short coming common to both conventional PCM and SLM techniques is the propensity to inadequately capture data on certain types of process variations that can propagate at various locations on a given wafer. Process variations can occur during many of the scores of process steps performed on a wafer during integrated circuit manufacture. Many of these are due to the dynamics of heat transfer across a flat disk. For example, during the formation of a thermal oxide layer on a given wafer, a band or ring of the thermal oxide may develop with a significant variation from the anticipated nominal thickness. The band itself may have a uniform thickness that deviates from the anticipated nominal thickness of the rest of the film or may exhibit a gradient. In either event, if the band of variable thickness does not form over one of the appropriate test structures fabricated on the wafer, the extent and impact of the area of process variation may not be adequately characterized so that its origin may be determined and appropriate modifications to the process flow may be made to eliminate it.
Some conventional process flows avoid the problem of degraded yield due to the impact of PCM fabrication on adjacent operational integrated circuits by utilizing dedicated test wafers upon which only test structures are fabricated. While this technique avoids the aforementioned yield problems, data acquired from dedicated test wafers does not necessarily correlate well with the behavior of the electrical circuits and the processes used to form them on actual production wafers.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.